As it offers advantages of bulk device electrical resistance reduction, bulk device thermal resistance reduction while maintaining low profile, the ability of making thin chips with a reduced substrate thickness, less than about 10 mils in thickness, of power semiconductor devices has become very desirable in the semiconductor industry. The following is a brief review of some prior arts for making thin semiconductor wafers. Typically semiconductor devices are formed on a wafer having a thick heavily doped substrate, with a thinner epitaxial layer formed on top. The active components of the semiconductor device are formed near the top surface of the wafer, in the epitaxial layer. The thick substrate provides stability and mechanical support for the wafer while it is being processed into semiconductor devices. However, especially for vertical power devices, the substrate adds resistance to the device, even when it is heavily doped. Thus, after front side processing of the wafer is finished, portions of the backside of the substrate are often ground away to thin the substrate. However, as the wafer grows thinner, the wafer becomes more fragile and difficult to handle, especially when the wafer is under 50 microns thick.
In a first prior art example a Dicing Before Grinding (DBG) system for making thin chips is briefly described here. In a first step the front side of a semiconductor wafer is diced, with a dicing blade, to a shallow partial dicing depth defining future individual chips. Next a tape-1 is press rolled onto the diced wafer front surface. Then the semiconductor wafer is flipped upside down and its back side is ground down, with a grinding head, till separation of the individual chips while still held onto tape-1. Next a tape-2 is press rolled onto the diced wafer back surface. Next the semiconductor wafer is flipped again to reveal its front side followed by tape-1 peel-off with the individual chips now held onto tape-2 instead. Then the separated albeit taped chips are transported to a wafer front side stacker for pick up and packaging of the individual chips. Besides being complicated and involving two transfer tapes, the DBG process does not allow for wafer back side processing after the back grinding.
A second prior art example involves a Wafer Support System (WSS) for making thin chips down to around 20 microns. In first step a semiconductor wafer is mounted back side up, with a UV-cured liquid adhesive, onto a stack of light to heat conversion (LTHC) release and support glass. The LTHC release is a coating on the support glass. Next the wafer back side is ground down to a desired thickness with a grinding wheel. While the ground wafer is still held to the assembly, back side semiconductor wafer processing can take place. Afterwards the assembly is flipped over and has its back side bonded onto a dicing tape held by a dicing frame. Next, the LTHC release, due to a focused laser irradiation through the support glass, is detached from the UV-cured liquid adhesive and the support glass. This allows removal of the support glass and peel off of the UV-cured liquid adhesive in following steps to reveal the already thinned wafer for further processing. Despite the advantage of allowing back side semiconductor wafer processing after wafer thinning, there remains the concern of process complication due to potential in-process out gassing from the LTHC release and the UV-cured liquid adhesive. Additionally, the associated proprietary processing equipment can be quite expensive.
FIG. 4 is a top plan view illustrating US patent application 20080207094, entitled “Method and apparatus for ultra thin wafer backside processing” published on Aug. 28, 2008, by Tao Feng et al. The apparatus 100 is for processing the backside 145 of an ultra thin wafer 140. The apparatus 100 comprises an outer ring 110 of generally toroidal configuration that is formed of any rigid material such as metal or a semiconductor. Outer ring 110 may have any configuration and preferably has a rectangular cross section for facilitating the use of the apparatus with a clamp. The outer ring 110 may be sized to accommodate therewithin a wafer 140. In an exemplary embodiment, the outer ring 110 may have an outer diameter of 8 inches to accommodate therewithin a 6-inch wafer. The apparatus 100 further comprises a high temperature grinding and/or dicing tape 120 affixed or otherwise adhered about the outer ring 110 on a bottom surface thereof. The outer ring 110 is operable to provide a holding mechanism for, and rigid support to, the high temperature tape 120. For this purpose, the outer ring 110 may also be formed in, and integrated with, other structures. Tape 120 may include a back grinding and/or dicing tape that can resist the temperatures associated with wafer backside processing such as metallization. During application, an ultra thin wafer or diced wafer is adhered to the high temperature tape 120 within the outer ring 110 for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Despite the advantage of allowing back side semiconductor wafer processing after wafer thinning, there remains the difficulty of handling the wafer when it has been back ground to a very thin level, say, a thickness less than about 2 mils as the semiconductor material can become quite frail. As a result, manufacturing process yield can be impacted.
FIG. 5 and FIG. 6 are respectively a bottom view and a cross sectional view illustrating U.S. Pat. No. 6,162,702, entitled “Self-supported ultra thin silicon wafer process” granted on Dec. 19, 2000. The U.S. Pat. No. 6,162,702 disclosed a silicon wafer 1 having an ultra thin central portion 2 that is supported by a circumferential rim 3 of thicker silicon. The central region is thinned by conventional means using conventional removal apparatus. As an alternative method, the central portion is removed using a photoresist mask or a combination of a photoresist mask, a hard mask and an etch. Along with the previously mentioned prior art, U.S. Pat. No. 6,162,702 can face the difficulty of handling the wafer after it has been thinned to a very low level, say, a thickness less than about 2 mils as the semiconductor material can become quite frail. Another disadvantage is that standard wafer handling equipment has to be modified considering the special structure with the circumferential rim. In summary, there remains the challenge of making ultra thin power semiconductor chips with post-thinning wafer processing steps while avoiding the difficulty of ultra thin wafer handling and usage of nonstandard wafer handling equipment.